Altera FPGA Designing with Quartus-II

מק"ט: #55700 | משך קורס: 24 שעות אק'

In this intense 3-days Course You will learn the most basics and useful think that FPGA Designer have to know for creating successful Design using Altera Quartus®II software.

הקורס פעיל לקבוצות מטעם ארגונים בלבד, ניתן לשלוח פנייה רק אם מדובר בקבוצה
*שדות חובה




In This day we will learn the basics features in the design flow using the Quartus® II software .
You will learn how to use the Quartus® II software v. 10.1 to develop an FPGA or CPLD design from initial design to device programming. You will create a new project, input new or existing design files, and compile your project. You’ll learn how to search for compilation information, use settings and assignments to adjust the results of compilation, and manage I/O-related assignments. You will also learn about using the TimeQuest timing analyzer, the path-based static timing analysis tool included with the Quartus II software. You will learn techniques to help you plan your design. You will employ Quartus II features that can help you achieve design goals faster. You will also learn how to plan and manage I/O assignments for your target device.



In this day we will constraint on the Timing analysis issues with the TimeQuest tool.
You will learn how to constrain & analyze a design for timing using the TimeQuest timing analyzer in the Quartus® II software v. 10.1. This includes understanding FPGA timing parameters, writing Synopsys Design Constraint (SDC) files, generating various timing reports in the TimeQuest timing analyzer & applying this knowledge to an FPGA design. Besides learning the basic requirements to ensure that your design meets timing, you will see how the TimeQuest timing analyzer makes it easy to create timing constraints to help you meet those requirements.



In this day we will constraint on the useful debug & analysis  tools when using Altera devices .
You will learn features of the Quartus® II software v. 10.1 that will enable you to analyze and debug your Altera® design. You will estimate FPGA power consumption using Quartus II power analysis tools. You will learn how to analyze simultaneous switching noise using the Simultaneous Switching Noise (SSN) Analyzer. You will verify design functionality using debugging tools available in the Quartus II software, such as the SignalTap® II embedded logic analyzer, SignalProbe, In-System Sources & Probes, & the Logic Analyzer Interface. You will learn to analyze and make changes to your design using the Chip Planner. You will be introduced to the System Console and related tools to debug your system using TCL based toolkits.



  • Make pre-project decisions to prepare for Quartus II design
  • Create, manage & compile Quartus II projects
  • Use Quartus II tools to view the results of compilation
  • Plan & manage device I/O assignments using Pin Planner
  • Use the basics of the TimeQuest timing tool
  • Review compilation results in various Quartus II software reports and graphical viewers
  • Understand the TimeQuest timing analyzer timing analysis design flow
  • Apply basic and complex timing constraints to an FPGA design
  • Analyze an FPGA design for timing using the TimeQuest timing analyzer
  • Write and manipulate SDC files for analysis and controlling the Quartus II compilation
  • Analyze power consumption with PowerPlay analyzer
  • Analyze signal integrity issues with SSN Analyzer
  • Debug designs in-system using SignalTap II ELA
  • Quickly route internal nodes to pins using SignalProbe without a full recompilation
  • Connect internal nodes to an external logic analyzer using Logic Analyzer Interface
  • View & edit embedded memory contents using In-System Memory Content Editor
  • Make incremental changes with Chip Planner
  • Perform low level system debug





תנאי קדם

  • Background in digital logic design

  • Ability to describe a hardware system using VHDL, Verilog or EDA schematic tool

  • Experience with PCs and the Windows operating system


משך הקורס

משך הקורס הינו 24 שעות



  •  Intro to Altera & Devices

  • Quartus II Feature Overview

  •  Design Methodology

  •  Quartus II Projects

  •  Design Entry

  •  Compilation

  •  Settings & Assignments

  •  I/O Planning

  •  Timing Analysis        

Hands on Training          


  • Exercise -1 : Project Management 

  • Exercise -2 : Design Entry   Exercise -3 : Compilation 

  • Exercise -4 : Settings & Assignments 

  • Exercise -5 : I/O Planning 

  • Exercise -6 : Timing Analysis