PCI Express

מק"ט: #43800 | משך קורס: 24 שעות אק'

The course provides a detailed and comprehensive understanding of the PCI Express technology including PCI Express 3.0. The course covers all aspects of the specification from a hardware design perspective and also discusses the software requirements of PCI Express implementations.
PCIE 3.0 and PCIE 2.0 main changes are described as well.
This course provides example implementations, and practical guidance that will give a running start on your design.

הקורס פעיל לקבוצות מטעם ארגונים בלבד, ניתן לשלוח פנייה רק אם מדובר בקבוצה
*שדות חובה


The participants will be able to specify performance, define architecture and design hardware platform and configure the configuration space.

קהל יעד


This in-depth course is hardware and software oriented. It describes all options and performance, and as a result it is useful for System Architecture as well



Legacy PCI – Plug and Play concept

  • Performance

  • Basic architecture

  • Memory, I/O, and  Configuration space

  • Configuration process

  • Data transfer

  • PCI to PCI Transparent Bridge concept

  • Posted & Non-Posted R/W


Introduction to PCI Express

  • Why new I/O architecture

  • Link and Lane definition

  • Root Complex, Switch & Endpoint definition

  • Layers overview (Transaction, Data & Physical)

  • Card specification (Electrical and Mechanical)

  • Advanced Switching (advanced peer to peer communication)


Mechanical Specification

  • Connector types

  • Add In Card form factor


Physical Layer (Electrical and Logical)

  • Electrical Sub Block

  • Card Specification

  • Design guidelines

  • Lanes

  • Link State machine

  • Link Training process

  • Configuration space – Link Capability


Data Link Layer Basics

  • Packet Types

  • Packet Format

  • Data Link Layer Packet (DLLP)

  • Timeout

  • Retry


Transaction Layer

  • Layering Overview

  • Transaction Types (Memory, I/O, Configuration, Messages)

  • TLP Header Format

  • Request Rules

  • Completion Rules

  • Maximum Packet Size 


System Architecture(QoS, Interrupts, Error Handling,   Reset)

  • ECRC

  • Message Type

  • Error Signaling

  • Flow Control

  • Quality of Service (QoS)

  • Interrupt Mechanism (INYx & MSI)

  • Intel 915G Chipset



Power (Power Management, Hot Plug)

  • Reset

  • Power Management (PM)

  • Slot Capability

  • Hot Plug - basics

  • Hot Plug/ Removal implementation           


Configuration Space

  • Type 0 Configuration Space

  • PCIe Capability Structure (inside legacy configuration space)

  • PCI Express Capabilities

  • Device Capabilities

  • Link Capabilities

  • Slot Capabilities

  • Root Complex

  • Extended capabilities

  • Advanced Error Reporting

  • Virtual Channel



  • PCIE 3.0 main features

  • Analysis of  NVIDIA Video Acceleration configuration Space

  • PCIE tracer (CATC) examples