Advanced Altera FPGA Designing with Quartus-II

מק"ט: #55000 | משך קורס: 24 שעות אק'

In this 3-day course you will learn the most advanced features of Quartus® II , we will constraint on Optimization issues and Advanced Timing Constraint And Analysis.
You will learn advanced features of the Quartus® II design software v.10.1 that will enable you to shorten your design cycle as well as improve your design performance and utilization. You will use the incremental compilation flow and LogicLock™ regions in the Quartus II software to reduce compile times and preserve performance on selected regions of your designs. You will obtain your design goals in the area of performance, resource usage and power consumption by using design strategies, HDL coding styles and Quartus II software settings. You will also learn how to manage compile times effectively. 
You will improve your proficiency in writing Synopsys Design Constraint (SDC) files and performing timing analysis using the TimeQuest timing analyzer in the Quartus® II software v. 10.1. You will write SDC files to constrain the more advanced types of interfaces and blocks used in today’s FPGA designs. You will then analyze these designs to verify proper operation and performance. You will also learn how to automate the process of constraining and analysis by writing customized Tcl script files.  

הקורס פעיל לקבוצות מטעם ארגונים בלבד, ניתן לשלוח פנייה רק אם מדובר בקבוצה
*שדות חובה
PDF version

מטרות הקורס

  • Define physical region constraints using LogicLock regions
  • Manage user-defined design partitions using the Quartus II incremental compilation flow Apply incremental compilation to the top-down & team-based design flows
  • Use Quartus II software settings and tools to improve internal & I/O timing, reduce logic resource usage & lower power consumption
  • Write Tcl script files to automate constraining and analysis of FPGA designs
  • Apply timing exceptions to real design situations
  • Properly constrain and analyze the following design situations: Source synchronous interfaces, External feedback designs, and High-speed interfaces containing dedicated SERDES hardware

תנאי קדם

  • Completion of "Altera Fpga Designing with  Quartus II "  course OR a working knowledge of the Quartus II software
  • Working knowledge of the TimeQuest timing analyzer and basic SDC commands
  • Experience with PCs and the Windows operating system

משך הקורס

משך הקורס הינו 24 שעות


  • Optimizing compilation time
  • Optimization aides
  • Optimizing area
  • Optimizing power
  • Optimizing performance 
  • SDC Review
  • Timing Analysis and Tcl 
  • Timing Exceptions
  • Source Synchronous Analysis
  • Feedback Designs
  • LVDS Timing Analysis


Hands on Training

  • Quartus II Incremental Compilation
  • Timing Optimization
  • Timing Optimization Using PLL
  • Multicycle Constraints for Clock-Enabled Designs
  • Source Synchronous Interfaces – Single Data Rate
  • Source Synchronous Interfaces – Double Data Rate
  • Constraining Feedback Designs
  • LVDS Timing Analysis
  • Optional: Timing Analysis and Tcl


לפי יצרן: