Advanced Altera FPGA Designing with Quartus-II
In this 3-day course you will learn the most advanced features of Quartus® II , we will constraint on Optimization issues and Advanced Timing Constraint And Analysis.
You will learn advanced features of the Quartus® II design software v.10.1 that will enable you to shorten your design cycle as well as improve your design performance and utilization. You will use the incremental compilation flow and LogicLock™ regions in the Quartus II software to reduce compile times and preserve performance on selected regions of your designs. You will obtain your design goals in the area of performance, resource usage and power consumption by using design strategies, HDL coding styles and Quartus II software settings. You will also learn how to manage compile times effectively.
You will improve your proficiency in writing Synopsys Design Constraint (SDC) files and performing timing analysis using the TimeQuest timing analyzer in the Quartus® II software v. 10.1. You will write SDC files to constrain the more advanced types of interfaces and blocks used in today’s FPGA designs. You will then analyze these designs to verify proper operation and performance. You will also learn how to automate the process of constraining and analysis by writing customized Tcl script files.