FPGA Timing Methodology using Synopsys Design Constraint - SDC

מק"ט: #55001 | משך קורס: 16 שעות אק'

In this 2-day course you will learn the Basics and must Methodology in Today’s FPGA design with Synopsys Design Constraint  (SDC), timing Constraint Format  , and how to insert and analyze timing Constraint

You will learn the basic understanding of timing analysis and how they impact our design, we will go over all kind of timing constraint and we will learn to build sdc files for constraining our FPGA design

You will learn how to verify the timing constraint Impact on our design, you will learn to do timing analysis and to know what are the options in case that our design is not closing Timing

*שדות חובה
PDF version


  • Understand the basics of Timing analysis
  • Build SDC files for constraining FPGA designs
  • Verify Timing on Designs using the FPGA Vendor Tools  

תנאי קדם

  • FPGA Designers who wants to have more experienced on Timing Issues

תנאי קדם

  • Working knowledge of  FPGA Vendor tools like Quartus P&R tools or equivalent
  • Working knowledge of the FPGA vendor timing analyzer and basic SDC commands
  • Experience with PCs and the Windows operating system
  • Working Knowledge with  HDL – advantage


  • Timing Analysis Basics
  • FPGA Timing Analyzer  basics
  • Analyze and know how to read Timing Report
  • Clock Constraint
  • Synchronous I/O constraint
  • Constraining Asynchronous Signals
  • Timing Exceptions
    • MCP – Multicycle constraints
    • False paths


Hands on Training

  • Exercise -1 : Introduction To Timing Analysis Tool
  • Exercise -2 : Timing Analysis :Clock Constraints
  • Exercise -1 : Timing Analysis : Synchronous I/O Constraints
  • Exercise -2 : Timing Analysis :Timing Exceptions & Analysis