SystemVerilog is the most popular technology in EDA Verification. It is an extension of the popular Verilog language, bringing a higher level of abstraction to design and verification. SystemVerilog provides a complete verification environment, employing Constraint Random Generation, Assertion Based Verification and Coverage Driven Verification. These methods improve dramatically the verification process. SystemVerilog also provides enhanced hardware-modeling features, which improve the RTL design productivity and simplify the design process.