SystemVerilog

מק"ט: #4919 | משך קורס: 40 שעות אק'

SystemVerilog is the most popular technology in EDA Verification. It is an extension of the popular Verilog language, bringing a higher level of abstraction to design and verification. SystemVerilog provides a complete verification environment, employing Constraint Random Generation, Assertion Based Verification and Coverage Driven Verification. These methods improve dramatically the verification process. SystemVerilog also provides enhanced hardware-modeling features, which improve the RTL design productivity and simplify the design process.

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מטרות

  • Design and verification SystemVerilog
  • Create a verification environment based on random generation and on functional coverage
  • SVA - SystemVerilog Assertions
  • Write test benches and build a verification environment

קהל יעד

Software and hardware designers who wish to be on the edge of the chip design industry.

תנאי קדם

Basic knowledge in Verilog or VHDL

נושאים

Introduction to SystemVerilog

  • The purpose of SystemVerilog
  • Backward compatibility with Verilog

 

Verification Methodology Overview

  • Traditional verification approaches
  • Issues with tradition verification approaches
  • The SystemVerilog solution
  • Introduction to Coverage Driven Verification (CDV) methodology

 

SystemVerilog Syntax

  • Data types
  • Arrays and queues
  • Data organization
  • Struct and union
  • Flow control
  • Tasks and functions

 

Driving and Receiving Data

  • Threads
  • synchronization
  • Interfaces
  • Modports
  • Clocking blocks

 

Object Oriented Programming (OOP)

  • OOP methodology overview
  • Classes
  • Properties and methods
  • Constructors
  • Protection
  • Inheritance

 

Constrained-Random Generation

  • Random variables
  • The randomize() function
  • Defining constraints

 

SVA – System verilog Assertions

  • Immediate
  • Sequences
  • Properties

 

Coverage

  • Coverage methodology
  • Different forms of coverage
  • Defining coverage groups
  • Defining coverage bins
  • Transition coverage
  • Cross coverage
  • Coverage options

 

Verification Testbench

  • Generators
  • Drivers
  • Monitors
  • Checkers
  • Reference Model
     
תגיות